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DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESSTM JITTER ATTENUATOR
ICS8741004
General Description
The ICS8741004 is a high performance Differential-to-LVDS/0.7V Differential Jitter HiPerClockSTM Attenuator designed for use in PCI ExpressTM systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS8741004 has 3 PLL bandwidth modes: 200kHz, 600kHz and 2MHz. The 200kHz mode will provide maximum jitter attenuation, but with higher PLL tracking skew and spread spectrum modulation from the motherboard synthesizer may be attenuated. The 600kHz provides an intermediate bandwidth that can easily track triangular spread profiles, while providing good jitter attenuation. The 2MHz bandwidth provides the best tracking skew and will pass most spread profiles, but the jitter attenuation will not be as good as the lower bandwidth modes. Because some 2.5Gb serdes have x20 multipliers while others have x25 multipliers, the ICS8741004 can be set for 1:1 mode or 5/4 multiplication mode (i.e. 100MHz input/125MHz output) using the F_SEL pins.
Features
* * * * * * * * * * *
Two LVDS and two 0.7V differential output pairs Bank A has two LVDS output pairs and Bank B has two 0.7V differential output pairs One differential clock input pair CLK, CLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL Output frequency range: 98MHz - 160MHz Input frequency range: 98MHz - 128MHz VCO range: 490MHz - 640MHz Cycle-to-cycle jitter: 35ps (maximum) Full 3.3V operating supply Three bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs 0C to 70C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
ICS
The ICS8741004 uses IDT's 3rd Generation FemtoClockTM PLL technology to achieve the lowest possible phase noise. The device is packaged in a 24 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards.
Pin Assignment
QA1 QA1 VDDO QA0 QA0 MR BW_SEL nc VDDA F_SELA VDD OEA 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 QB1 QB1 VDDO QB0 QB0 IREF F_SELB OEB GND GND CLK CLK
PLL Bandwidth
BW_SEL 0 = PLL Bandwidth: ~200kHz Float = PLL Bandwidth: ~600kHz (default) 1 = PLL Bandwidth: ~2MHz
ICS8741004
24-Lead TSSOP 4.4mm x 7.8mm x 0.925mm package body G Package Top View
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Block Diagram
OEA
Pullup
F_SELA Pulldown QA0
BW_SEL Float
0 = ~200kHz Float = ~400kHz 1 = ~800kHz
F_SELA 0 /5 (default) 1 /4
QA0 QA1
CLK Pulldown
CLK
Pullup
Phase Detector
VCO
490 - 640 MHz
QA1
QB0
M = /5 (fixed)
F_SELB 0 /5 (default) 1 /4
QB0
QB1
QB1 F_SELB Pulldown MR Pulldown
IREF
Pullup
OEB
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Table 1. Pin Descriptions
Number 1, 24 3, 22 4, 5 Name QA1, QA1 VDDO QA0, QA0 Output Power Output Type Description Differential output pair. LVDS interface levels. Output supply pins. Differential output pair. LVDS interface levels. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Q[Ax:Bx] to go LOW and the inverted outputs Q[Ax:Bx] to go HIGH. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. PLL Bandwidth input. LVCMOS/LVTTL interface levels. See Table 3B. No connect. Analog supply pin. Pulldown Frequency select pins for QAx/QAx outputs. LVCMOS/LVTTL interface levels. See Table 3C. Core supply pin. Pullup Pulldown Pullup Output enable for QAx pins. When HIGH, QAx/QAx outputs are enabled. When LOW, the QAx/QAx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. See Table 3A. Non-inverting differential clock input. Inverting differential clock input. Power supply ground. Pullup Output enable for QBx pins. When HIGH, QBx/QBx outputs are enabled. When LOW, the QBx/QBx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. See Table 3A. Frequency select pins for QBx/QBx outputs. LVCMOS/LVTTL interface levels. See Table 3C. A fixed precision resistor (RREF = 475) from this pin to ground provides a reference current used for differential current-mode QB0/nQB0 clock outputs. Differential output pair. HCSL interface levels. Differential output pair. HCSL interface levels.
6
MR
Input
Pulldown
7 8 9 10 11 12 13 14 15, 16 17
BW_SEL nc VDDA F_SELA VDD OEA CLK CLK GND OEB
Input Unused Power Input Power Input Input Input Power Input
Pullup/ Pulldown
18 19 20, 21 23, 24
F_SELB IREF QB0, QB0 QB1, QB1
Input Input Output Output
Pulldown
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
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Function Tables
Table 3A. Output Enable Function Table
Inputs OEA 0 1 OEB 0 1 Outputs QA[0:1]/QA[0:1] Hi-Z Enabled QB[0:1]/QB[0:1] Hi-Z Enabled
Table 3B. PLL Bandwidth Function Table
Input BW_SEL 0 Float 1 PLL Bandwidth ~200kHz ~600kHz (default) ~2MHz
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG Rating 4.6V -0.5V to VDD + 0.5V -0.5V to VDDO + 0.5V 82.3C/W (0 mps) -65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V 5%, TA = 0C to 70C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Positive Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 VDD - 0.12 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 VDD 3.465 45 12 80 Units V V V mA mA mA
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Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V 5%, TA = 0C to 70C
Symbol Parameter OEA, OEB, MR, F_SELA, F_SELB BW_SEL OEA, OEB, MR, F_SELA, F_SELB BW_SEL VIM IIH Input Mid Voltage BW_SEL F_SELA, F_SELB, MR, BW_SEL OEA, OEB MR, F_SELA, F_SELB, OEA, OEB, BW_SEL VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 Test Conditions Minimum 2 VDD - 0.3 -0.3 -0.3 VDD/2 - 0.1 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 +0.3 VDD/2 + 0.1 150 5 Units V V V V V A A A A
VIH
Input High Voltage
VIL
Input Low Voltage
Input High Current
IIL
Input Low Current
Table 4C. Differential DC Characteristics, VDD = VDDO = 3.3V 5%, TA = 0C to 70C
Symbol IIH Parameter CLK Input High Current CLK CLK IIL Input Low Current CLK VPP VCMR Peak-to-Peak Voltage Common Mode Input Voltage; NOTE 1 Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 0.15 GND + 0.5 1.3 VDD - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
NOTE 1: Common mode input voltage is defined as VIH.
Table 4D. LVDS DC Characteristics, VDD = VDDO = 3.3V 5%, TA = 0C to 70C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change 1.2 1.35 Test Conditions Minimum 290 Typical 390 Maximum 490 50 1.5 50 Units mV mV V mV
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AC Electrical Characteristics
Table 5. 0.7V Differential AC Characteristics, VDD = VDDO = 3.3V 5%, TA = 0C to 70C
Parameter fMAX tjit(cc) tsk(b) VHIGH VLOW VOVS VUDS Vrb VCROSS VCROSS Symbol Output Frequency Cycle-to-Cycle Jitter; NOTE 1 Bank Skew, NOTE 2 Output Voltage High Output Voltage Low Max. Voltage, Overshoot Min. Voltage, Undershoot Ringback Voltage Absolute Crossing Voltage Total Variation of VCROSS over all edges Output Rise/Fall Time Rise/Fall Time Variation Rise/Fall Matching Output Duty Cycle QBx/QBx QBx/QBx QBx/QBx QBx/QBx QBx/QBx QBx/QBx QBx/QBx QBx/QBx QAx/QAx tR / tF tRFM odc QBx/QBx QBx/QBx 48 @ 0.7V Swing @ 0.7V Swing measured between 0.175V to 0.525V 20% to 80% 175 250 250 -0.3 0.2 550 140 700 600 125 20 52 530 -150 VHIGH + 0.35 Test Conditions Minimum 98 Typical Maximum 160 35 30 870 Units MHz ps ps ps ps V V V mV mV ps ps ps % %
tR / tF
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.
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Parameter Measurement Information
VDD, VDDO VDDA
,
33 49.9 33
50
Measurement Point
VDD, VDDO
SCOPE
Qx
VDDA
3.3V5% POWER SUPPLY + Float GND -
HCSL
50
2pF Measurement Point
LVDS
nQx
GND RREF = 475
49.9
2pF
3.3V HCSL Output Load AC Test Circuit
3.3V LVDS Output Load AC Test Circuit
VDD
QX0 QX0
V Cross Points
CLK
OD
QX1 QX1
CLK
V
OS
tsk(b)
GND
Where X is either Bank A or Bank B
Differential Input Level
Bank Skew
QA[0:1], QB[0:1] QA[0:1], QB[0:1]
QA[0:1], QB[0:1] QA[0:1], QB[0:1]
t PW
t
PERIOD
tcycle n
tjit(cc) = tcycle n - tcycle n+1 1000 Cycles
Cycle-to-Cycle Jitter
IDTTM / ICSTM PCI EXPRESSTM JITTER ATTENUATOR
tcycle n+1
odc =
t PW t PERIOD
x 100%
Output Duty Cycle/Pulse Width/Period
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Parameter Measurement Information, continued
0.525V Clock 0.175V Outputs
0.525V VSW I N G 0.175V Clock Outputs 20%
80%
80% VOD 20% tF
tR
tF
tR
HCSL Output Rise/Fall Time
LVDS Output Rise/Fall Time
VDD
VDD

out
out
out
VOS/ VOS
Differential Output Voltage Setup
Offset Voltage Setup
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DC Input
LVDS
DC Input
out
100
VOD/ VOD
LVDS
ICS8741004 DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESSTM JITTER ATTENUATOR
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8741004 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a 0.01F bypass capacitor should be connected to each VDDA pin.
3.3V VDD .01F VDDA .01F 10F 10
Figure 1. Power Supply Filtering
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input CLK
V_REF nCLK C1 0.1u
R2 1K
Figure 2. Single-Ended Signal Driving Differential Input
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Differential Clock Input Interface
The CLK /CLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS CLK/CLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V 3.3V 1.8V Zo = 50 Zo = 50 CLK Zo = 50 Zo = 50 nCLK nCLK CLK 3.3V
LVPECL HiPerClockS Input
R1 50 R2 50
HiPerClockS Input
LVHSTL IDT HiPerClockS LVHSTL Driver
R1 50 R2 50
R2 50
Figure 3A. HiPerClockS CLK/CLK Input Driven by an IDT HiPerClockS LVHSTL Driver
Figure 3B. HiPerClockS CLK/CLK Input Driven by a 3.3V LVPECL Driver
3.3V 3.3V 3.3V R3 125 Zo = 50 CLK CLK Zo = 50 nCLK R1 100 R4 125 3.3V 3.3V Zo = 50
LVPECL
R1 84 R2 84
HiPerClockS Input
Zo = 50
nCLK
LVDS
Receiver
Figure 3C. HiPerClockS CLK/CLK Input Driven by a 3.3V LVPECL Driver
Figure 3D. HiPerClockS CLK/CLK Input Driven by a 3.3V LVDS Driver
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Recommendations for Unused Input and Output Pins Inputs:
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
Outputs:
Differential Outputs
All unused differential outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
LVDS Outputs
All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, we recommend that there is no trace attached.
LVDS Driver Termination
A general LVDS interface is shown in Figure 4. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs.
3.3V 3.3V 50
LVDS Driver R1 100
+
-
50
100 Differential Transmission Line
Figure 4. Typical LVDS Driver Termination
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Recommended Termination
Figure 5A is the recommended termination for applications which require the receiver and driver to be on a separate PCB. All traces should be 50 impedance.
Figure 5A. Recommended Termination
Figure 5B is the recommended termination for applications which require a point to point connection and contain the driver and
receiver on the same PCB. All traces should all be 50 impedance.
Figure 5B. Recommended Termination
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Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8741004. Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS741004 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * * * Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (45mA + 12mA) = 197.5mW Power (LVDS_output)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 80mA = 227.2mW Power (HCSL_output)MAX = 45.65mW * 2 = 91.3mW
Total Power_MAX = (3.465V, with all outputs switching) = 197.5mW + 277.2mW + 91.3mW = 556mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 82.3C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.556W * 82.3C/W = 115.8C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer).
Table 6. Thermal Resistance JA for 24 Lead TSSOP, Forced Convection
JA Vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 82.3C/W 1 78.0C/W 2.5 75.9C/W
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3. Calculations and Equations. The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 6.
VDD O
VOU T
RL
50
IC
Figure 6. LVHSTL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load and a termination
voltage of VCCO - 2V. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Pd_H = (VOH_MAX /RL) * (VDD_MAX - VOH_MAX) Pd_L = (VOL_MIN /RL) * (VDD_MAX - VOL_MIN) Pd_H = (0.85V /50) * (3.465V - 0.87V) = 44.1mW Pd_L = (0.15V/50) * 0.15V = 0.45mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 45mW
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Reliability Information
Table 7. JA vs. Air Flow Table for a 24 Lead TSSOP
JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 82.3C/W 1 78.0C/W 2.5 75.9C/W
Transistor Count
The transistor count for ICS8741004 is: 1318
Package Outline and Package Dimension
Package Outline - G Suffix for 24 Lead TSSOP Table 8. Package Dimensions
All Dimensions in Millimeters Symbol Minimum Maximum N 24 A 1.20 A1 0.5 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 7.90 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 0 8 aaa 0.10 Reference Document: JEDEC Publication 95, MO-153
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Ordering Information
Table 9. Ordering Information
Part/Order Number 8741004AG 8741004AGT 8741004AGLF 8741004AGLFT Marking ICS8741004AG ICS8741004AG ICS8741004AGLF ICS8741004AGLF Package 24 Lead TSSOP 24 Lead TSSOP "Lead-Free" 24 Lead TSSOP "Lead-Free" 24 Lead TSSOP Shipping Packaging Tray 2500 Tape & Reel Tray 2500 Tape & Reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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(c) 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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